Charge-coupled devices, often referred to as "CCDs", are used in various fields such as solid state imaging, analog signal processing, and memories for both analog and digital signals. An interline CCD sensor has an image sensing area, and at least one horizontal shift register. The image sensing area has independent photo sites that convert incident light into electrons which are transferred along the horizontal shift register towards an output region. There has been a constant push to reduce the driving clock voltages within CCDs. This means that the width, i.e. the direction perpendicular to that of charge transfer of these devices becomes increasingly larger to maintain adequate charge capacity. Therefore, it becomes necessary to taper this width down towards the output region so as to maintain a low output node capacitance for high electrometer sensitivity and low noise. This raises concerns involving devices having narrow channels and/or short lengths in their output regions of the horizontal registers. Narrow channels and short lengths individually can result in what are referred to as two dimensional (2-D) effects. Taken in combination, 2-D effects, such as narrow channel and short length, can create three dimensional (3-D) effects. The concern when tapering down the width of these wide CCDs is that undesirable potential wells and/or barriers may be inadvertently created by 2-D and 3-D effects that can impede charge flow and reduce charge-transfer efficiency. Some examples of recent attempts to overcome these problems are disclosed in U.S. Pat. Nos. 5,286,989, 5,220,185 and 5,239,192. From the most relevant, 5,239,192, 3-D device simulation shows that this approach still results in the formation of a pocket under the last stage (the stage adjacent to the output gate, OG), and does not provide an adequate drift field, thereby leading to poor transfer efficiency. Also, this method (as described in U.S. Pat. No. 5,239,192) requires an extra masking and an implant step which can reduce yield and increase manufacturing costs. Therefore, there remains a need within the design of the output region to alleviate the aforementioned problems. The present invention describes such a structure that eliminates these aforementioned difficulties.